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If the instruction processing is split into 6 phases
then the pipelined CPU will have 6 different stages for the execution of the
sub phases.
The six stages are as follows :
The six stages are as follows :
- Fetch Instruction : Instruction are fetched from the memory into a temporary buffer before it gets executed.
- Decode Instruction :The intstruction is decoded by the CPU so that the necessary OP codes and operands can be determined .
- Calculate Operand :It is based on the addressing scheme used, either operands are directly provided in the instruction or the effective address has to be calculated.
- Fetch Operand :Once the address is calculated,the operands need to be fetched from the address that was calculated. This is done in this phase.
- Execute Instruction :The instruction can now be executed .
- Write Operand :Once the instruction is executed, the result from the execution needs to be stored or written back in the memory.
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